# Phase 4 - First CPU

## Context

This phase connects fetch, decode, arithmetic, register-file, and writeback into a minimal
non-pipelined CPU. It executes straight-line arithmetic programs from instruction BRAM.

## Goals

- Build the first integrated datapath.
- Learn how BRAM latency shapes control flow.
- Verify architectural state changes instruction by instruction.

## New Concepts

- BRAM: block RAM, dedicated on-chip FPGA memory with synchronous access.
- PC: program counter, the address of the current or next instruction.
- Writeback: stage where a result is committed to the register file.
- CPI: cycles per instruction.

## How To Think About It

This is not a performance exercise. It is an integration exercise. The goal is to make
one instruction at a time retire correctly while respecting real memory latency.

## Learning Tasks

- Draw the fetch/execute FSM.
- Decide exactly when PC advances.
- Trace a short program and record expected register state after each instruction.

## Pitfalls

- Treating BRAM like a combinational array.
- Updating PC while a multi-cycle M operation is still in progress.
- Writing back results for instructions that should not write a register.

## Tooling And Testing

- Start with very small programs and known final register values.
- Use simulation waveforms before ILA.
- Add a visible "halt" or terminal condition for test programs.

## References

- AMD/Xilinx block memory documentation: https://docs.xilinx.com/
- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
- Digital design FSM overview: https://www.chipverify.com/verilog/verilog-fsm