# Phase 2.2 - Optional VIO Validation

## Context

The register file is simple enough that simulation is usually sufficient, but VIO can
teach practical debug techniques on real FPGA state.

## Goals

- Practice observing and driving register-file signals in hardware.
- Confirm reset/write/read expectations after synthesis.
- Learn when hardware debug is worth the overhead.

## New Concepts

- Probe: signal connected to debug IP for observation.
- Debug visibility: whether a net survives optimization and can be inspected.
- Hardware Manager: Vivado tool for programming and interacting with the FPGA.

## How To Think About It

Use VIO here only as a learning exercise. Do not make it a habit to replace systematic
simulation with manual poking.

## Learning Tasks

- Select a minimal set of probes: addresses, write data, write enable, read outputs.
- Compare one same-cycle read/write case with the simulator.
- Observe how a clocked write appears relative to your VIO actions.

## Pitfalls

- Over-instrumenting and making the debug design harder than the actual module.
- Forgetting that manual tests rarely cover corner cases.
- Treating VIO as evidence of complete correctness.

## Tooling And Testing

- Keep the VIO wrapper separate from the synthesizable register-file module.
- Remove or isolate debug IP before building later phases.
- Check resource utilization with and without debug IP.

## References

- Vivado debug documentation: https://docs.xilinx.com/
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- LowRISC style guide: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md