# Phase 6 - Load/Store

## Context

Load/store connects the CPU to data memory and later to memory-mapped devices. RISC-V is
a load/store architecture: arithmetic works on registers, memory access is explicit.

## Goals

- Add data BRAM at `0x8000_0000`.
- Define and use the D-bus contract.
- Support word, byte, and halfword memory operations.

## New Concepts

- LSU: load/store unit, responsible for address generation and data formatting.
- D-bus: data-side memory request/response channel.
- Byte lane: one of the four bytes in a 32-bit word.
- Write strobe: byte-enable mask for sub-word stores.

## How To Think About It

Memory operations are protocol transactions. Address alignment, byte selection, sign
extension, response timing, and error classification all matter.

## Learning Tasks

- Draw how a byte store updates one lane of a 32-bit word.
- Decide how the LSU detects misalignment before bus issue.
- Trace a load from execute through response and writeback.

## Pitfalls

- Returning unshifted data for byte/halfword loads.
- Treating misalignment as a bus error instead of an architectural exception.
- Forgetting stores do not write back to the register file.

## Tooling And Testing

- Test all byte offsets within a word.
- Use memory dumps or waveform inspection for store byte lanes.
- Add maximum cycle timeouts to catch hung bus handshakes.

## References

- RISC-V load/store semantics: https://riscv.org/technical/specifications/
- AMD/Xilinx block RAM documentation: https://docs.xilinx.com/
- AXI-Lite valid/ready concepts for handshake comparison: https://developer.arm.com/documentation/ihi0022/latest