# Phase 5.2 - Jump Instructions

## Context

Jumps provide unconditional control transfer and function-call mechanics. `jal` is
PC-relative; `jalr` jumps through a register plus immediate.

## Goals

- Implement `jal` and `jalr`.
- Store PC + 4 into the destination register.
- Verify call and return sequences.

## New Concepts

- Return address: address of the instruction after the call.
- Indirect jump: target comes from a register rather than only the instruction.
- J-type immediate: immediate format used by `jal`.
- Calling convention: software agreement for argument, return, and saved registers.

## How To Think About It

`jal` and `jalr` are both "write link, then redirect PC." The redirect source differs;
the writeback behavior is shared.

## Learning Tasks

- Hand-trace a call and return using `ra` (`x1`).
- Verify `jalr` target bit 0 clearing.
- Learn which registers the RISC-V ABI uses for calls.

## Pitfalls

- Writing the jump target instead of PC + 4 into `rd`.
- Mishandling `rd = x0`, which should discard the link.
- Forgetting `jalr` is commonly used for returns and function pointers.

## Tooling And Testing

- Test `jal`, `jalr`, and `jalr x0, ra, 0` return style.
- Use objdump to confirm labels assemble to expected offsets.
- Inspect register writeback and PC change in the same trace.

## References

- RISC-V unprivileged ISA, jumps: https://riscv.org/technical/specifications/
- RISC-V ELF psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual