# FPGA-Core

Custom RISC-V CPU core built from scratch in SystemVerilog. Starts as RV32IM,
grows to RV32IMA + Sv32 + M/S/U privilege en route to booting Linux.

## Target

- Board: Digilent Arty A7 100T (xc7a100tcsg324-1)
- Toolchain: Vivado 2025.2 or later
- Language: SystemVerilog
- ISA: end target **RV32IMA + Zicsr + Zifencei + M/S/U privilege + Sv32**
  (Linux-capable). Built incrementally — see `ROADMAP.md`.
- Clock: 50 MHz (100 MHz xtal ÷ 2 via MMCM)

## Architecture

"Single-cycle" logical model (no pipeline registers), Harvard architecture
(separate instruction/data BRAM). The combinational ALU and a multi-cycle M
unit (DSP-based multiply, iterative divide) sit side by side; the datapath
stalls on M-unit and BRAM accesses. Inter-stage signals are typed structs in
`rv32_pkg.sv` — the same structs become pipeline registers when the core is
pipelined later (Phase 13, optional).

## Memory Map

| Address Range             | Region                                       |
|---------------------------|----------------------------------------------|
| `0x0000_0000–0x0FFF_FFFF` | reserved boot aperture (Phase 14: 16 MB SPI flash at low end) |
| `0x1000_0000–0x1000_0FFF` | MMIO (UART; later: timer, PLIC)              |
| `0x2000_0000–0x2000_FFFF` | instruction BRAM (64 KB)                     |
| `0x8000_0000–0x8000_FFFF` | data BRAM (64 KB) → DRAM in Phase 14         |

Reset PC = `0x2000_0000`.

UART registers (split layout):

| Address       | Access | Meaning                                      |
|---------------|--------|----------------------------------------------|
| `0x1000_0000` | W      | TX data — byte to send                       |
| `0x1000_0004` | R      | RX data — pops one byte from RX FIFO         |
| `0x1000_0008` | R      | status — bit0 = `tx_busy`, bit1 = `rx_valid` |

## Building

Requires:
- Vivado 2025.2 or later
- RISC-V GCC toolchain — multilib `riscv64-unknown-elf-gcc`. March string
  evolves with the implementation: `rv32im` (Phase 8) →
  `rv32im_zicsr_zifencei` (Phase 9) → `rv32ima_zicsr_zifencei` (Phase 12).
- `riscv-tests` (for compliance verification from Phase 8.5)
- Serial terminal (minicom/picocom/PuTTY) at 115200 8N1

Open `FPGA-Core.xpr` in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.

## Roadmap

See `ROADMAP.md` for the full phased build plan.

## Current Phase

Phase 0 — Architecture contract (package definitions + block diagram)

## References

- [RISC-V ISA Spec Vol 1 (Unprivileged)](https://riscv.org/technical/specifications/)
- [RISC-V ISA Spec Vol 2 (Privileged)](https://riscv.org/technical/specifications/)
- [Arty A7 Reference Manual](https://digilent.com/reference/programmable-logic/arty-a7/reference-manual)