# create_project.tcl — generate FPGA/vivado/FPGA-Core.xpr
#
# Usage (from the repo root):
#   vivado -mode batch -source FPGA/vivado/create_project.tcl
#
# Or from inside FPGA/vivado/:
#   vivado -mode batch -source create_project.tcl
#
# Then open the resulting .xpr in the Vivado GUI. To regenerate from scratch,
# delete FPGA-Core.xpr and its sibling *.cache / *.runs / *.hw / *.sim /
# *.ip_user_files / *.gen directories, then re-run.

set script_dir [file normalize [file dirname [info script]]]
set fpga_dir   [file normalize "$script_dir/.."]
set proj_name  "FPGA-Core"
set part       "xc7a100tcsg324-1"

if {[file exists "$script_dir/$proj_name.xpr"]} {
    puts "Project already exists: $script_dir/$proj_name.xpr"
    puts "Delete it (and its sibling *.cache, *.runs, ... dirs) first."
    return
}

create_project $proj_name $script_dir -part $part

set_property target_language    Verilog [current_project]
set_property simulator_language Mixed   [current_project]

# RTL and testbenches are added as references (not copied) so the source of
# truth stays in git, not inside the .xpr. Passing a directory makes Vivado
# recursively pick up all HDL files under it.
add_files                "$fpga_dir/rtl"
add_files -fileset sim_1 "$fpga_dir/tb"

set xdc_files [glob -nocomplain "$fpga_dir/constraints/*.xdc"]
if {[llength $xdc_files] > 0} {
    add_files -fileset constrs_1 $xdc_files
}

update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

puts "Created $script_dir/$proj_name.xpr"