# Phase 7.2 - UART RX Module

## Context

The RX module samples an asynchronous serial input and reconstructs bytes. It must handle
input synchronization and sampling near bit centers.

## Goals

- Build a standalone receiver.
- Learn oversampling and input synchronization.
- Produce a received byte plus valid indication.

## New Concepts

- Asynchronous input: signal not aligned to the FPGA clock.
- Synchronizer: flip-flop chain reducing metastability risk.
- Metastability: temporary uncertain state when sampling near an input transition.
- Oversampling: sampling multiple times per bit period to find stable centers.

## How To Think About It

RX is less forgiving than TX because the external signal is not clocked by your FPGA.
Respect clock-domain boundary hygiene even for a slow UART pin.

## Learning Tasks

- Draw how a start bit is detected.
- Decide the sample point for each data bit.
- Define what `valid` means and how it is cleared.

## Pitfalls

- Sampling the RX pin without synchronization.
- Sampling too close to bit transitions.
- Losing bytes because there is no buffering or clear valid/ready policy.

## Tooling And Testing

- Simulate with ideal frames and then slightly shifted frames.
- Test receiver behavior with back-to-back bytes.
- Add a FIFO later if software cannot poll fast enough.

## References

- Metastability overview: https://www.01signal.com/verilog-design/clockdomains/crossing-basics/
- Nandland UART receiver tutorial: https://nandland.com/uart-serial-port-module/
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual