# Phase 3 - Decoder

## Context

The decoder translates a 32-bit instruction word into control signals. It is where the
binary ISA becomes meaningful hardware intent.

## Goals

- Decode RV32I/RV32M instruction fields and immediates.
- Produce structured control output for later datapath integration.
- Learn to verify against assembler-generated encodings.

## New Concepts

- Opcode: primary instruction-class field.
- funct3/funct7: secondary fields that refine instruction meaning.
- Immediate: constant encoded inside an instruction, often split across bits.
- Illegal instruction: encoding the core does not implement or that is invalid.

## How To Think About It

The decoder is a classifier. It should not perform ALU work; it should describe what
work the datapath must perform and which operands/control paths are needed.

## Learning Tasks

- Draw bit layouts for R, I, S, B, U, and J formats.
- Hand-decode several assembled instructions.
- Decide where illegal instruction detection lives and how it reports failures.

## Pitfalls

- Misplacing B-type and J-type immediate bits.
- Forgetting sign extension on immediates.
- Treating all unknown encodings as harmless NOPs.

## Tooling And Testing

- Use assembler/objdump as a reference for encodings.
- Build tests around every format, not just every mnemonic.
- Keep decoder tests independent from ALU or register-file behavior.

## References

- RISC-V unprivileged ISA instruction formats: https://riscv.org/technical/specifications/
- RISC-V opcode map: https://github.com/riscv/riscv-opcodes
- GNU binutils RISC-V documentation: https://sourceware.org/binutils/docs/