Establish the repository as a documentation-first plan for a custom
SystemVerilog RISC-V CPU targeting the Digilent Arty A7 100T.
Add the initial README, roadmap, and contributor guidance that define the
starting RV32IM direction, Vivado/RISC-V toolchain expectations, basic
SystemVerilog conventions, and the phased path from an architecture contract
toward a Linux-capable SoC.
This commit intentionally contains planning and interface direction only; RTL,
firmware, testbenches, and Vivado project files are left for later phases.
