Refine tutorial roadmap references

Tutorial/phase-04-first-cpu/phase-04-01-fetch-datapath-integration.md

@@ -27,7 +27,8 @@ more than minimizing cycles.
 
 - Write a cycle-by-cycle timeline for a simple `addi` instruction.
 - Write a cycle-by-cycle timeline for a multiply/divide instruction.
-- Decide what happens on illegal instruction before Phase 9 traps exist.
+- Confirm the pre-Phase 9 illegal-instruction behavior: halt the core and expose
+  the offending PC and instruction word to the testbench.
 
 ## Pitfalls
 
@@ -46,4 +47,3 @@ more than minimizing cycles.
 - RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
 - Vivado simulation documentation: https://docs.xilinx.com/
 - Project F memory initialization: https://projectf.io/posts/initialize-memory-in-verilog/
-

Tutorial/phase-06-load-store/phase-06-03-ila-memory-bus.md

@@ -44,5 +44,4 @@ which side violated the contract.
 
 - Vivado ILA documentation: https://docs.xilinx.com/
 - Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
-- Wishbone spec for bus-debug vocabulary: https://cdn.opencores.org/downloads/wbspec_b4.pdf
-
+- AXI-Lite valid/ready concepts for bus-debug vocabulary: https://developer.arm.com/documentation/ihi0022/latest

Tutorial/phase-06-load-store/phase-06.md

@@ -45,5 +45,4 @@ extension, response timing, and error classification all matter.
 
 - RISC-V load/store semantics: https://riscv.org/technical/specifications/
 - AMD/Xilinx block RAM documentation: https://docs.xilinx.com/
-- Wishbone bus spec for handshake comparison: https://cdn.opencores.org/downloads/wbspec_b4.pdf
-
+- AXI-Lite valid/ready concepts for handshake comparison: https://developer.arm.com/documentation/ihi0022/latest

Tutorial/phase-07-uart-mmio/phase-07-03-bus-decoder-mmio.md

@@ -45,5 +45,4 @@ semantics becomes painful. Document behavior precisely.
 
 - OSDev MMIO overview: https://wiki.osdev.org/Memory_Mapped_Registers_in_C/C%2B%2B
 - RISC-V privileged spec for access faults later: https://riscv.org/technical/specifications/
-- Wishbone bus spec: https://cdn.opencores.org/downloads/wbspec_b4.pdf
-
+- AXI-Lite valid/ready concepts for comparison: https://developer.arm.com/documentation/ihi0022/latest

Tutorial/phase-09-csrs-traps/phase-09.md

@@ -29,7 +29,8 @@ software to inspect the cause, handle it, and resume or terminate.
 ## Learning Tasks
 
 - Draw the exact state updates on trap entry.
-- Write a table of each exception source and its `mcause`.
+- Write a table of each exception source and its `mcause`, then compare it with
+  the trap-cause decisions in the roadmap.
 - Understand which PC is saved for each exception type.
 
 ## Pitfalls
@@ -49,4 +50,3 @@ software to inspect the cause, handle it, and resume or terminate.
 - RISC-V privileged architecture spec: https://riscv.org/technical/specifications/
 - RISC-V CSR instruction semantics: https://riscv.org/technical/specifications/
 - RISC-V educational trap handling notes: https://osblog.stephenmarz.com/
-

Tutorial/phase-14-flash-dram/phase-14.md

@@ -24,9 +24,13 @@ persistent boot storage and much larger RAM, so this phase adds flash boot and D
 This is the first major SoC integration phase. External memory is not a simple array:
 latency varies, calibration matters, and reset sequencing becomes important.
 
+The concrete map follows the roadmap: the 16 MB on-board SPI flash is mapped at
+`0x0000_0000-0x00FF_FFFF` inside the reserved boot aperture, and the 256 MB DDR3L
+DRAM replaces data BRAM at `0x8000_0000-0x8FFF_FFFF`.
+
 ## Learning Tasks
 
-- Understand the Arty A7 memory devices and their address ranges.
+- Understand the Arty A7 memory devices and the fixed address ranges above.
 - Draw boot flow from reset to flash fetch to DRAM copy to jump.
 - Decide how I-bus and D-bus arbitrate for DRAM.
 
@@ -47,4 +51,3 @@ latency varies, calibration matters, and reset sequencing becomes important.
 - Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
 - AMD/Xilinx MIG documentation: https://docs.xilinx.com/
 - JEDEC DDR background: https://www.jedec.org/standards-documents/focus/memory-module-design
-

Tutorial/phase-16-linux-boot-contract/phase-16.md

@@ -28,6 +28,9 @@ wrong, Linux often just hangs early with little output.
 
 - Read the RISC-V Linux boot protocol and list required register state.
 - Draft a device tree matching your memory map and interrupt topology.
+- Use the modern CPU ISA properties: `riscv,isa-base = "rv32i"` and
+  `riscv,isa-extensions = "i", "m", "a", "zicsr", "zifencei"`. Keep the legacy
+  `riscv,isa = "rv32ima_zicsr_zifencei"` string only as a compatibility fallback.
 - Decide whether the first Linux attempt uses direct M-mode or OpenSBI.
 
 ## Pitfalls
@@ -47,4 +50,3 @@ wrong, Linux often just hangs early with little output.
 - RISC-V Linux boot protocol: https://docs.kernel.org/arch/riscv/boot.html
 - RISC-V device-tree CPU bindings: https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/cpus.yaml
 - OpenSBI: https://github.com/riscv-software-src/opensbi
-