Refine tutorial roadmap references

Tutorial/phase-14-flash-dram/phase-14.md

@@ -24,9 +24,13 @@ persistent boot storage and much larger RAM, so this phase adds flash boot and D
 This is the first major SoC integration phase. External memory is not a simple array:
 latency varies, calibration matters, and reset sequencing becomes important.
 
+The concrete map follows the roadmap: the 16 MB on-board SPI flash is mapped at
+`0x0000_0000-0x00FF_FFFF` inside the reserved boot aperture, and the 256 MB DDR3L
+DRAM replaces data BRAM at `0x8000_0000-0x8FFF_FFFF`.
+
 ## Learning Tasks
 
-- Understand the Arty A7 memory devices and their address ranges.
+- Understand the Arty A7 memory devices and the fixed address ranges above.
 - Draw boot flow from reset to flash fetch to DRAM copy to jump.
 - Decide how I-bus and D-bus arbitrate for DRAM.
 
@@ -47,4 +51,3 @@ latency varies, calibration matters, and reset sequencing becomes important.
 - Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
 - AMD/Xilinx MIG documentation: https://docs.xilinx.com/
 - JEDEC DDR background: https://www.jedec.org/standards-documents/focus/memory-module-design
-