Refine tutorial roadmap references

2026-04-28 12:40:53 +02:00
parent c1ffb0ee41
commit fdf9292b8a
7 changed files with 15 additions and 13 deletions
@@ -45,5 +45,4 @@ extension, response timing, and error classification all matter.

 - RISC-V load/store semantics: https://riscv.org/technical/specifications/
 - AMD/Xilinx block RAM documentation: https://docs.xilinx.com/
- Wishbone bus spec for handshake comparison: https://cdn.opencores.org/downloads/wbspec_b4.pdf
-
+- AXI-Lite valid/ready concepts for handshake comparison: https://developer.arm.com/documentation/ihi0022/latest