Refine tutorial roadmap references

Tutorial/phase-06-load-store/phase-06-03-ila-memory-bus.md

@@ -44,5 +44,4 @@ which side violated the contract.
 
 - Vivado ILA documentation: https://docs.xilinx.com/
 - Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
-- Wishbone spec for bus-debug vocabulary: https://cdn.opencores.org/downloads/wbspec_b4.pdf
-
+- AXI-Lite valid/ready concepts for bus-debug vocabulary: https://developer.arm.com/documentation/ihi0022/latest

Tutorial/phase-06-load-store/phase-06.md

@@ -45,5 +45,4 @@ extension, response timing, and error classification all matter.
 
 - RISC-V load/store semantics: https://riscv.org/technical/specifications/
 - AMD/Xilinx block RAM documentation: https://docs.xilinx.com/
-- Wishbone bus spec for handshake comparison: https://cdn.opencores.org/downloads/wbspec_b4.pdf
-
+- AXI-Lite valid/ready concepts for handshake comparison: https://developer.arm.com/documentation/ihi0022/latest