Refine tutorial roadmap references

Tutorial/phase-04-first-cpu/phase-04-01-fetch-datapath-integration.md

@@ -27,7 +27,8 @@ more than minimizing cycles.
 
 - Write a cycle-by-cycle timeline for a simple `addi` instruction.
 - Write a cycle-by-cycle timeline for a multiply/divide instruction.
-- Decide what happens on illegal instruction before Phase 9 traps exist.
+- Confirm the pre-Phase 9 illegal-instruction behavior: halt the core and expose
+  the offending PC and instruction word to the testbench.
 
 ## Pitfalls
 
@@ -46,4 +47,3 @@ more than minimizing cycles.
 - RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
 - Vivado simulation documentation: https://docs.xilinx.com/
 - Project F memory initialization: https://projectf.io/posts/initialize-memory-in-verilog/
-