Add BIOS and tiny kernel roadmap phases

Tutorial/phase-15-atomics/phase-15.md

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+# Phase 15 - A Extension
+
+## Context
+
+The RISC-V A extension adds atomic memory operations. Mainline Linux expects atomics for
+locking, reference counts, futexes, and synchronization.
+
+## Goals
+
+- Implement LR/SC.
+- Implement AMO read-modify-write instructions.
+- Run RV32A tests before Linux work.
+
+## New Concepts
+
+- Atomic operation: memory operation that appears indivisible to other agents.
+- LR/SC: load-reserved/store-conditional pair.
+- Reservation: remembered address that allows a later store-conditional to succeed.
+- AMO: atomic memory operation combining load, operation, and store.
+
+## How To Think About It
+
+In a single-hart, single-master system atomics are conceptually simple. The value is in
+building the right architectural behavior now so the Linux path is realistic later.
+
+## Learning Tasks
+
+- Study success and failure cases for `sc.w`.
+- Decide when the reservation is cleared.
+- List AMO operations and their signed/unsigned comparison behavior.
+
+## Pitfalls
+
+- Returning the wrong success code from `sc.w`.
+- Forgetting AMOs return the original memory value.
+- Assuming single-hart shortcuts will remain valid if DMA or another master is added.
+
+## Tooling And Testing
+
+- Run `rv32ua` tests from riscv-tests or architectural tests.
+- Use memory traces to verify read-modify-write ordering.
+- Test reservation clearing on stores to the reserved address.
+
+## References
+
+- RISC-V unprivileged ISA, A extension: https://riscv.org/technical/specifications/
+- riscv-tests: https://github.com/riscv-software-src/riscv-tests
+- Linux atomic operations documentation: https://docs.kernel.org/core-api/wrappers/atomic_t.html
+