Add BIOS and tiny kernel roadmap phases

README.md

@@ -19,16 +19,16 @@ grows to RV32IMA + Sv32 + M/S/U privilege en route to booting Linux.
 unit (DSP-based multiply, iterative divide) sit side by side; the datapath
 stalls on M-unit and BRAM accesses. Inter-stage signals are typed structs in
 `rv32_pkg.sv` — the same structs become pipeline registers when the core is
-pipelined later (Phase 13, optional).
+pipelined later (Phase 16, optional).
 
 ## Memory Map
 
 | Address Range             | Region                                       |
 |---------------------------|----------------------------------------------|
-| `0x0000_0000–0x0FFF_FFFF` | reserved boot aperture (Phase 14: 16 MB SPI flash at low end) |
+| `0x0000_0000–0x0FFF_FFFF` | reserved boot aperture (Phase 17: 16 MB SPI flash at low end) |
 | `0x1000_0000–0x1000_0FFF` | MMIO (UART; later: timer, PLIC)              |
 | `0x2000_0000–0x2000_FFFF` | instruction BRAM (64 KB)                     |
-| `0x8000_0000–0x8000_FFFF` | data BRAM (64 KB) → DRAM in Phase 14         |
+| `0x8000_0000–0x8000_FFFF` | data BRAM (64 KB) → DRAM in Phase 17         |
 
 Reset PC = `0x2000_0000`.
 
@@ -46,7 +46,7 @@ Requires:
 - Vivado 2025.2 or later
 - RISC-V GCC toolchain — multilib `riscv64-unknown-elf-gcc`. March string
   evolves with the implementation: `rv32im` (Phase 8) →
-  `rv32im_zicsr_zifencei` (Phase 9) → `rv32ima_zicsr_zifencei` (Phase 12).
+  `rv32im_zicsr_zifencei` (Phase 12) → `rv32ima_zicsr_zifencei` (Phase 15).
 - `riscv-tests` (for compliance verification from Phase 8.5)
 - Serial terminal (minicom/picocom/PuTTY) at 115200 8N1