Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

Tutorial/phase-06-load-store/phase-06.md

@@ -0,0 +1,49 @@
+# Phase 6 - Load/Store
+
+## Context
+
+Load/store connects the CPU to data memory and later to memory-mapped devices. RISC-V is
+a load/store architecture: arithmetic works on registers, memory access is explicit.
+
+## Goals
+
+- Add data BRAM at `0x8000_0000`.
+- Define and use the D-bus contract.
+- Support word, byte, and halfword memory operations.
+
+## New Concepts
+
+- LSU: load/store unit, responsible for address generation and data formatting.
+- D-bus: data-side memory request/response channel.
+- Byte lane: one of the four bytes in a 32-bit word.
+- Write strobe: byte-enable mask for sub-word stores.
+
+## How To Think About It
+
+Memory operations are protocol transactions. Address alignment, byte selection, sign
+extension, response timing, and error classification all matter.
+
+## Learning Tasks
+
+- Draw how a byte store updates one lane of a 32-bit word.
+- Decide how the LSU detects misalignment before bus issue.
+- Trace a load from execute through response and writeback.
+
+## Pitfalls
+
+- Returning unshifted data for byte/halfword loads.
+- Treating misalignment as a bus error instead of an architectural exception.
+- Forgetting stores do not write back to the register file.
+
+## Tooling And Testing
+
+- Test all byte offsets within a word.
+- Use memory dumps or waveform inspection for store byte lanes.
+- Add maximum cycle timeouts to catch hung bus handshakes.
+
+## References
+
+- RISC-V load/store semantics: https://riscv.org/technical/specifications/
+- AMD/Xilinx block RAM documentation: https://docs.xilinx.com/
+- Wishbone bus spec for handshake comparison: https://cdn.opencores.org/downloads/wbspec_b4.pdf
+