Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

Tutorial/phase-05-control-flow/phase-05-01-branch-instructions.md

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+# Phase 5.1 - Branch Instructions
+
+## Context
+
+Branches compare two registers and conditionally update PC to a PC-relative target. They
+enable loops and conditionals.
+
+## Goals
+
+- Implement `beq`, `bne`, `blt`, `bge`, `bltu`, and `bgeu`.
+- Learn signed and unsigned branch comparisons.
+- Verify target calculation and fall-through behavior.
+
+## New Concepts
+
+- PC-relative addressing: target is computed from current PC plus immediate.
+- Branch comparator: dedicated comparison logic for branch conditions.
+- B-type immediate: split immediate format used by branch instructions.
+- Taken branch: branch condition true, PC becomes target.
+
+## How To Think About It
+
+Separate three questions: what is the target, is the condition true, and which PC should
+be used next? Debugging is easier when those are visible independently.
+
+## Learning Tasks
+
+- Decode a B-type immediate by hand.
+- Build test cases where signed and unsigned comparisons differ.
+- Trace a loop from initialization through exit.
+
+## Pitfalls
+
+- Forgetting branch offsets are multiples of 2 bytes in the encoding.
+- Comparing signed values with unsigned operators.
+- Counting loop iterations incorrectly because PC update timing is unclear.
+
+## Tooling And Testing
+
+- Use assembler-generated branch encodings.
+- In waveforms, inspect PC, immediate, comparator result, and next PC.
+- Include backward and forward branch targets.
+
+## References
+
+- RISC-V unprivileged ISA, branch instructions: https://riscv.org/technical/specifications/
+- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual
+- RISC-V opcode data: https://github.com/riscv/riscv-opcodes
+

Tutorial/phase-05-control-flow/phase-05-02-jump-instructions.md

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+# Phase 5.2 - Jump Instructions
+
+## Context
+
+Jumps provide unconditional control transfer and function-call mechanics. `jal` is
+PC-relative; `jalr` jumps through a register plus immediate.
+
+## Goals
+
+- Implement `jal` and `jalr`.
+- Store PC + 4 into the destination register.
+- Verify call and return sequences.
+
+## New Concepts
+
+- Return address: address of the instruction after the call.
+- Indirect jump: target comes from a register rather than only the instruction.
+- J-type immediate: immediate format used by `jal`.
+- Calling convention: software agreement for argument, return, and saved registers.
+
+## How To Think About It
+
+`jal` and `jalr` are both "write link, then redirect PC." The redirect source differs;
+the writeback behavior is shared.
+
+## Learning Tasks
+
+- Hand-trace a call and return using `ra` (`x1`).
+- Verify `jalr` target bit 0 clearing.
+- Learn which registers the RISC-V ABI uses for calls.
+
+## Pitfalls
+
+- Writing the jump target instead of PC + 4 into `rd`.
+- Mishandling `rd = x0`, which should discard the link.
+- Forgetting `jalr` is commonly used for returns and function pointers.
+
+## Tooling And Testing
+
+- Test `jal`, `jalr`, and `jalr x0, ra, 0` return style.
+- Use objdump to confirm labels assemble to expected offsets.
+- Inspect register writeback and PC change in the same trace.
+
+## References
+
+- RISC-V unprivileged ISA, jumps: https://riscv.org/technical/specifications/
+- RISC-V ELF psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
+- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual
+

Tutorial/phase-05-control-flow/phase-05.md

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+# Phase 5 - Branches And Jumps
+
+## Context
+
+This phase adds control flow. The CPU stops being a straight-line executor and gains
+loops, conditionals, function calls, and returns.
+
+## Goals
+
+- Implement conditional branches.
+- Implement `jal` and `jalr`.
+- Learn PC selection and control-transfer testing.
+
+## New Concepts
+
+- Branch target: destination address for a taken branch.
+- Fall-through: next sequential PC, usually PC + 4.
+- Link register: register receiving return address for calls.
+- Control hazard: later pipeline issue where fetched instructions may be wrong.
+
+## How To Think About It
+
+Control flow is just PC update logic plus optional register writeback. Keep the
+comparison, target calculation, and PC selection clearly separated.
+
+## Learning Tasks
+
+- Hand-compute branch and jump targets from instruction immediates.
+- Trace a simple loop and count taken versus not-taken branches.
+- Understand why `jalr` clears bit 0 of the target address.
+
+## Pitfalls
+
+- Off-by-four errors between current PC and next PC.
+- Using unsigned comparison for signed branches.
+- Forgetting that `jal`/`jalr` write PC + 4 to `rd`.
+
+## Tooling And Testing
+
+- Test both taken and not-taken paths for every branch type.
+- Use short loops with known iteration counts.
+- Probe PC source selection in simulation and ILA.
+
+## References
+
+- RISC-V branch and jump semantics: https://riscv.org/technical/specifications/
+- RISC-V assembly examples: https://github.com/riscv-non-isa/riscv-asm-manual
+- Computer architecture control flow overview: https://www.nand2tetris.org/
+