Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

Tutorial/phase-03-decoder/phase-03-01-instruction-decoder.md

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+# Phase 3.1 - Instruction Decoder
+
+## Context
+
+This subphase creates the combinational decoder module that turns raw instruction bits
+into `decode_out_t` fields.
+
+## Goals
+
+- Decode source/destination registers, immediates, ALU operation, memory operation, and branch type.
+- Identify legal versus illegal instructions.
+- Verify all instruction formats with known encodings.
+
+## New Concepts
+
+- Sign extension: copying a sign bit into higher bits to preserve signed value.
+- Zero extension: filling upper bits with zero.
+- Control signal: a signal that chooses what hardware action occurs.
+- Decode table: mapping from instruction fields to operation semantics.
+
+## How To Think About It
+
+Decoder bugs often look like random CPU bugs later. Invest heavily here. If an immediate
+bit is wrong, the ALU and branch logic can be perfect and the program will still fail.
+
+## Learning Tasks
+
+- Create a checklist for each instruction family and expected decode fields.
+- For each immediate format, manually reconstruct the value from bit positions.
+- Decide how `fence`, `fence.i`, CSR, `ecall`, and `ebreak` are represented before traps exist.
+
+## Pitfalls
+
+- Copying immediate extraction logic without understanding bit order.
+- Missing `jalr`'s low-bit clearing rule later in execute/control flow.
+- Letting default decode outputs accidentally describe a valid NOP.
+
+## Tooling And Testing
+
+- Generate encodings with the RISC-V assembler, not by hand alone.
+- Use objdump to verify that your test words are the instructions you think they are.
+- Add negative tests for illegal encodings.
+
+## References
+
+- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
+- RISC-V opcode repository: https://github.com/riscv/riscv-opcodes
+- GNU assembler manual: https://sourceware.org/binutils/docs/as/
+

Tutorial/phase-03-decoder/phase-03.md

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+# Phase 3 - Decoder
+
+## Context
+
+The decoder translates a 32-bit instruction word into control signals. It is where the
+binary ISA becomes meaningful hardware intent.
+
+## Goals
+
+- Decode RV32I/RV32M instruction fields and immediates.
+- Produce structured control output for later datapath integration.
+- Learn to verify against assembler-generated encodings.
+
+## New Concepts
+
+- Opcode: primary instruction-class field.
+- funct3/funct7: secondary fields that refine instruction meaning.
+- Immediate: constant encoded inside an instruction, often split across bits.
+- Illegal instruction: encoding the core does not implement or that is invalid.
+
+## How To Think About It
+
+The decoder is a classifier. It should not perform ALU work; it should describe what
+work the datapath must perform and which operands/control paths are needed.
+
+## Learning Tasks
+
+- Draw bit layouts for R, I, S, B, U, and J formats.
+- Hand-decode several assembled instructions.
+- Decide where illegal instruction detection lives and how it reports failures.
+
+## Pitfalls
+
+- Misplacing B-type and J-type immediate bits.
+- Forgetting sign extension on immediates.
+- Treating all unknown encodings as harmless NOPs.
+
+## Tooling And Testing
+
+- Use assembler/objdump as a reference for encodings.
+- Build tests around every format, not just every mnemonic.
+- Keep decoder tests independent from ALU or register-file behavior.
+
+## References
+
+- RISC-V unprivileged ISA instruction formats: https://riscv.org/technical/specifications/
+- RISC-V opcode map: https://github.com/riscv/riscv-opcodes
+- GNU binutils RISC-V documentation: https://sourceware.org/binutils/docs/
+