Replace stale tutorial reference links

Tutorial/phase-00-architecture-contract/phase-00-01-systemverilog-package.md

@@ -43,7 +43,6 @@ definitions. If a signal is private to one module, keep it private.
 
 ## References
 
-- SystemVerilog packages and typedefs: https://verificationguide.com/systemverilog/systemverilog-package/
+- SystemVerilog packages and typedefs: https://www.chipverify.com/systemverilog/systemverilog-package
 - LowRISC SystemVerilog style: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
 - RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
-

Tutorial/phase-00-architecture-contract/phase-00.md

@@ -47,7 +47,6 @@ datapath. Bias toward clarity and explicitness, not clever compression.
 
 ## References
 
-- SystemVerilog IEEE overview: https://www.accellera.org/downloads/standards/systemverilog
+- Accellera IEEE standards downloads: https://www.accellera.org/downloads/ieee
 - LowRISC style guide: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
 - RISC-V specifications: https://riscv.org/technical/specifications/
-

Tutorial/phase-01-alu-m-unit/phase-01-01-combinational-alu.md

@@ -44,6 +44,5 @@ interpretation explicit in your design notes and tests.
 ## References
 
 - RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
-- SystemVerilog signed arithmetic notes: https://www.chipverify.com/systemverilog/systemverilog-data-types
+- SystemVerilog types, operators, and expressions: https://systemverilog.dev/2.html
 - Verilator warnings guide: https://verilator.org/guide/latest/warnings.html
-

Tutorial/phase-07-uart-mmio/phase-07-03-bus-decoder-mmio.md

@@ -43,6 +43,6 @@ semantics becomes painful. Document behavior precisely.
 
 ## References
 
-- OSDev MMIO overview: https://wiki.osdev.org/Memory_Mapped_Registers_in_C/C%2B%2B
+- Memory-mapped I/O overview: https://en.wikipedia.org/wiki/Memory-mapped_I/O
 - RISC-V privileged spec for access faults later: https://riscv.org/technical/specifications/
 - AXI-Lite valid/ready concepts for comparison: https://developer.arm.com/documentation/ihi0022/latest

Tutorial/phase-07-uart-mmio/phase-07.md

@@ -45,5 +45,4 @@ and peripheral register file translate those into device behavior.
 
 - Digilent Arty A7 USB-UART notes: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
 - RISC-V platform-level interrupt spec for later context: https://github.com/riscv/riscv-plic-spec
-- OSDev MMIO overview: https://wiki.osdev.org/Memory_Mapped_Registers_in_C/C%2B%2B
+- Memory-mapped I/O overview: https://en.wikipedia.org/wiki/Memory-mapped_I/O
-

Tutorial/phase-10-timer/phase-10.md

@@ -44,6 +44,5 @@ coordinate compare logic, pending state, enable bits, global interrupt enable, a
 ## References
 
 - RISC-V privileged architecture spec: https://riscv.org/technical/specifications/
-- RISC-V ACLINT specification: https://github.com/riscv-non-isa/riscv-aclint
+- RISC-V ACLINT specification: https://github.com/riscvarchive/riscv-aclint
 - Linux timekeeping background: https://docs.kernel.org/timers/
-

Tutorial/phase-14-flash-dram/phase-14.md

@@ -50,4 +50,4 @@ DRAM replaces data BRAM at `0x8000_0000-0x8FFF_FFFF`.
 
 - Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
 - AMD/Xilinx MIG documentation: https://docs.xilinx.com/
-- JEDEC DDR background: https://www.jedec.org/standards-documents/focus/memory-module-design
+- DDR3 SDRAM background: https://en.wikipedia.org/wiki/DDR3_SDRAM