Replace stale tutorial reference links

Tutorial/phase-01-alu-m-unit/phase-01-01-combinational-alu.md

@@ -44,6 +44,5 @@ interpretation explicit in your design notes and tests.
 ## References
 
 - RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
-- SystemVerilog signed arithmetic notes: https://www.chipverify.com/systemverilog/systemverilog-data-types
+- SystemVerilog types, operators, and expressions: https://systemverilog.dev/2.html
 - Verilator warnings guide: https://verilator.org/guide/latest/warnings.html
-