Replace stale tutorial reference links

2026-04-28 12:56:05 +02:00
parent fdf9292b8a
commit 91ca63cf73
7 changed files with 7 additions and 12 deletions
@@ -44,6 +44,5 @@ interpretation explicit in your design notes and tests.
 ## References

 - RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
- SystemVerilog signed arithmetic notes: https://www.chipverify.com/systemverilog/systemverilog-data-types
+- SystemVerilog types, operators, and expressions: https://systemverilog.dev/2.html
 - Verilator warnings guide: https://verilator.org/guide/latest/warnings.html
-