Replace stale tutorial reference links

2026-04-28 12:56:05 +02:00
parent fdf9292b8a
commit 91ca63cf73
7 changed files with 7 additions and 12 deletions
@@ -47,7 +47,6 @@ datapath. Bias toward clarity and explicitness, not clever compression.

 ## References

- SystemVerilog IEEE overview: https://www.accellera.org/downloads/standards/systemverilog
+- Accellera IEEE standards downloads: https://www.accellera.org/downloads/ieee
 - LowRISC style guide: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
 - RISC-V specifications: https://riscv.org/technical/specifications/
-