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Replace stale tutorial reference links

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Renat Nurgaliyev
2026-04-28 12:56:05 +02:00
parent fdf9292b8a
commit 91ca63cf73
7 changed files with 7 additions and 12 deletions
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Tutorial/phase-00-architecture-contract/phase-00-01-systemverilog-package.md
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@@ -43,7 +43,6 @@ definitions. If a signal is private to one module, keep it private.
## References
- SystemVerilog packages and typedefs: https://verificationguide.com/systemverilog/systemverilog-package/
- SystemVerilog packages and typedefs: https://www.chipverify.com/systemverilog/systemverilog-package
- LowRISC SystemVerilog style: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
Tutorial/phase-00-architecture-contract/phase-00.md
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@@ -47,7 +47,6 @@ datapath. Bias toward clarity and explicitness, not clever compression.
## References
- SystemVerilog IEEE overview: https://www.accellera.org/downloads/standards/systemverilog
- Accellera IEEE standards downloads: https://www.accellera.org/downloads/ieee
- LowRISC style guide: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
- RISC-V specifications: https://riscv.org/technical/specifications/