Add FPGA project workspace layout

2026-04-28 14:30:50 +02:00
parent e8631501e8
commit 329610807e
20 changed files with 210 additions and 18 deletions
@@ -37,7 +37,7 @@ state stored, what changes each clock, what can wait, and what happens on an exc

 ## Tooling And Testing

- Keep the diagram in `docs/` and update it when interfaces change.
+- Keep the diagram in `Docs/` and update it when interfaces change.
 - Compare waveform signal names against the diagram after each integration phase.
 - Use the diagram as a checklist when adding ILA probes.