Add FPGA project workspace layout

2026-04-28 14:30:50 +02:00
parent e8631501e8
commit 329610807e
20 changed files with 210 additions and 18 deletions
@@ -0,0 +1,6 @@
+# Software/fw/
+
+Bare-metal firmware: `crt0.S`, linker script, and the first C programs that
+run on the CPU. Also where `riscv-tests` integration lives.
+
+**Phases:** 8 (GCC toolchain, first C program, `riscv-tests`).