Add FPGA project workspace layout

This commit is contained in:
2026-04-28 14:30:50 +02:00
parent e8631501e8
commit 329610807e
20 changed files with 210 additions and 18 deletions
+5
View File
@@ -0,0 +1,5 @@
# Software/
Software that runs on the CPU: bare-metal firmware, BIOS, and kernels.
Built with the RISC-V GCC toolchain (`riscv64-unknown-elf-gcc`). The `march`
string evolves with the implemented ISA — see `CLAUDE.md`.
+6
View File
@@ -0,0 +1,6 @@
# Software/bios/
BIOS / monitor: an interactive ROM program that talks over UART to peek/poke
memory, dump registers, and load programs into RAM. Includes the ELF loader.
**Phases:** 9 (BIOS monitor), 10 (ELF loader over UART).
+6
View File
@@ -0,0 +1,6 @@
# Software/fw/
Bare-metal firmware: `crt0.S`, linker script, and the first C programs that
run on the CPU. Also where `riscv-tests` integration lives.
**Phases:** 8 (GCC toolchain, first C program, `riscv-tests`).
+7
View File
@@ -0,0 +1,7 @@
# Software/kernel/
Kernels that run on the core. Starts as a tiny custom kernel for learning
trap/scheduling/syscalls; later hosts the Linux device tree, OpenSBI, and
mainline Linux build artifacts.
**Phases:** 11 (tiny kernel), 19 (Linux boot contract), 20 (Linux).