Add FPGA project workspace layout
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# Software/
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Software that runs on the CPU: bare-metal firmware, BIOS, and kernels.
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Built with the RISC-V GCC toolchain (`riscv64-unknown-elf-gcc`). The `march`
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string evolves with the implemented ISA — see `CLAUDE.md`.
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# Software/bios/
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BIOS / monitor: an interactive ROM program that talks over UART to peek/poke
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memory, dump registers, and load programs into RAM. Includes the ELF loader.
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**Phases:** 9 (BIOS monitor), 10 (ELF loader over UART).
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# Software/fw/
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Bare-metal firmware: `crt0.S`, linker script, and the first C programs that
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run on the CPU. Also where `riscv-tests` integration lives.
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**Phases:** 8 (GCC toolchain, first C program, `riscv-tests`).
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# Software/kernel/
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Kernels that run on the core. Starts as a tiny custom kernel for learning
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trap/scheduling/syscalls; later hosts the Linux device tree, OpenSBI, and
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mainline Linux build artifacts.
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**Phases:** 11 (tiny kernel), 19 (Linux boot contract), 20 (Linux).
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