Add FPGA project workspace layout

README.md

@@ -50,7 +50,19 @@ Requires:
 - `riscv-tests` (for compliance verification from Phase 8.5)
 - Serial terminal (minicom/picocom/PuTTY) at 115200 8N1
 
-Open `FPGA-Core.xpr` in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.
+FPGA sources (RTL, testbenches, constraints, BRAM init files, and the Vivado
+project script) live under `FPGA/`. Software that runs on the core (firmware,
+BIOS, kernels) lives under `Software/`. The Vivado project itself is **not**
+committed — generate it from the script and then open it:
+
+```sh
+vivado -mode batch -source FPGA/vivado/create_project.tcl
+# then open FPGA/vivado/FPGA-Core.xpr in the Vivado GUI
+```
+
+Synthesis and implementation target the xc7a100tcsg324-1. RTL sources in
+`FPGA/rtl/` and testbenches in `FPGA/tb/` are added to the project as
+references — do not let Vivado copy them in.
 
 ## Roadmap