Add FPGA project workspace layout

2026-04-28 14:30:50 +02:00
parent e8631501e8
commit 329610807e
20 changed files with 210 additions and 18 deletions
@@ -0,0 +1,5 @@
+# FPGA/rtl/top/
+
+Top-level modules and SoC integration: clock/reset wrapping (MMCM, reset
+synchronizer), bus arbitration, address decode, and the board-level top that
+maps to the Arty A7 pins.