Add FPGA project workspace layout

2026-04-28 14:30:50 +02:00
parent e8631501e8
commit 329610807e
20 changed files with 210 additions and 18 deletions
@@ -0,0 +1,4 @@
+# FPGA/rtl/core/
+
+CPU core modules: ALU, M unit, decoder, register file, fetch, LSU, datapath,
+and (later) CSR file and MMU. Module names follow `rv32_<block>`.