Add FPGA project workspace layout

2026-04-28 14:30:50 +02:00
parent e8631501e8
commit 329610807e
20 changed files with 210 additions and 18 deletions
@@ -0,0 +1,4 @@
+# FPGA/rtl/
+
+Synthesizable SystemVerilog source. One module per file, filename matches
+module name (e.g. `rv32_alu.sv`).