Add FPGA project workspace layout

FPGA/rtl/README.md

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+# FPGA/rtl/
+
+Synthesizable SystemVerilog source. One module per file, filename matches
+module name (e.g. `rv32_alu.sv`).

FPGA/rtl/core/README.md

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+# FPGA/rtl/core/
+
+CPU core modules: ALU, M unit, decoder, register file, fetch, LSU, datapath,
+and (later) CSR file and MMU. Module names follow `rv32_<block>`.

FPGA/rtl/periph/README.md

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+# FPGA/rtl/periph/
+
+Memory-mapped peripherals: UART (Phase 7), CLINT timer (Phase 13), PLIC
+(Phase 14), and any future devices. Each peripheral is a slave on the D-bus.

FPGA/rtl/pkg/README.md

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+# FPGA/rtl/pkg/
+
+Shared SystemVerilog packages — the type contract for the design.
+`rv32_pkg.sv` (enums, stage-boundary structs, bus payloads) lives here.

FPGA/rtl/top/README.md

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+# FPGA/rtl/top/
+
+Top-level modules and SoC integration: clock/reset wrapping (MMCM, reset
+synchronizer), bus arbitration, address decode, and the board-level top that
+maps to the Arty A7 pins.