Label roadmap phase difficulty
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@@ -5,6 +5,24 @@
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---
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## Scope Guide
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Each phase is marked with a learning-scope label:
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- **Easy/fun** — good weekend/evening work. These phases have visible progress,
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tight feedback loops, and form a complete worthwhile project even if you stop
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before the Linux work.
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- **Hard stretch** — still rewarding, but expect deeper debugging, more spec
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reading, and longer gaps between visible milestones.
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- **Overkill/hard** — Linux-capable SoC work. Valuable if you want the full
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summit, but too much to treat as the baseline definition of success.
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Recommended casual target: reach Phase 8, where GCC-built C runs on your CPU and
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`riscv-tests` gives you confidence in the ISA implementation. Everything after
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that is enrichment or a long-term expedition.
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---
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## Memory Map (target — fixed in Phase 0, evolves through Phase 14)
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```
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@@ -21,7 +39,7 @@ stable across phases.
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---
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## Phase 0 — Architecture Contract
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## Phase 0 — Architecture Contract [Easy/fun]
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### 0.1 — SystemVerilog Package
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What: Create a `.sv` package file with enums (ALU operations, opcode types, branch
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@@ -49,7 +67,7 @@ source of truth when things get complex.
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---
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## Phase 1 — ALU + M Unit
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## Phase 1 — ALU + M Unit [Easy/fun]
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### 1.1 — Combinational ALU + Simulation
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What: Build a combinational ALU that handles all RV32I arithmetic/logic ops
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@@ -101,7 +119,7 @@ Future role: VIO familiarity pays off throughout the project.
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---
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## Phase 2 — Register File
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## Phase 2 — Register File [Easy/fun]
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### 2.1 — Register File Module + Simulation
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What: Build the RISC-V register file — 32 registers, each 32 bits wide. Two read
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@@ -125,7 +143,7 @@ for a register file since the logic is simple.
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---
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## Phase 3 — Decoder
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## Phase 3 — Decoder [Easy/fun]
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### 3.1 — Instruction Decoder + Simulation
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What: A combinational module that takes a raw 32-bit instruction word and produces
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@@ -152,7 +170,7 @@ decoder and a new field to the struct. The structure of the decoder doesn't chan
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---
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## Phase 4 — First CPU ("It's Alive")
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## Phase 4 — First CPU ("It's Alive") [Easy/fun]
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### 4.1 — Fetch + Datapath Integration
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What: Create an instruction BRAM initialized from a .mem file, mapped at
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@@ -199,7 +217,7 @@ Knowing how to use it well is arguably the most important FPGA debug skill.
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---
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## Phase 5 — Branches and Jumps (Control Flow)
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## Phase 5 — Branches and Jumps (Control Flow) [Easy/fun]
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### 5.1 — Branch Instructions
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What: Add a branch comparator (separate from the ALU — it checks rs1 vs rs2 for
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@@ -235,7 +253,7 @@ Future role: Final. These instructions don't change.
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---
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## Phase 6 — Load/Store (Data Memory)
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## Phase 6 — Load/Store (Data Memory) [Easy/fun]
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### 6.1 — Word Load/Store (lw, sw)
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What: Add a data BRAM mapped at `0x8000_0000` (64 KB) and a load/store unit.
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@@ -323,7 +341,7 @@ errors). ILA on the bus lets you see exactly what's happening each cycle.
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---
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## Phase 7 — Memory-Mapped UART
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## Phase 7 — Memory-Mapped UART [Easy/fun]
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### 7.1 — UART TX Module
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What: A standalone UART transmitter. Baud rate 115200, 8 data bits, no parity,
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@@ -392,7 +410,7 @@ screen.
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---
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## Phase 8 — GCC Toolchain Integration
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## Phase 8 — GCC Toolchain Integration [Easy/fun]
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### 8.1 — Linker Script + Startup Code
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What: Write a linker script that tells GCC where your instruction memory, data
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@@ -492,7 +510,7 @@ becomes regression coverage for the rest of the project.
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---
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## Phase 9 — CSRs + M-Mode Trap Handling
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## Phase 9 — CSRs + M-Mode Trap Handling [Hard stretch]
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What: Add Control and Status Registers (mstatus, mtvec, mepc, mcause, mtval, mie,
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mip) and the CSR instructions (csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci). Add
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@@ -509,7 +527,7 @@ plus S-mode (supervisor mode), which you'll add later.
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---
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## Phase 10 — Timer
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## Phase 10 — Timer [Hard stretch]
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What: Implement mtime (a free-running 64-bit counter) and mtimecmp (comparison
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register). When mtime >= mtimecmp, a timer interrupt fires.
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@@ -520,7 +538,7 @@ validates that the trap handling from Phase 9 actually works end-to-end.
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---
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## Phase 11 — Interrupt Controller
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## Phase 11 — Interrupt Controller [Hard stretch]
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What: Build a minimal PLIC (Platform-Level Interrupt Controller) or a simplified
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version. Connect UART RX as an interrupt source. Implement interrupt priority and
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@@ -532,7 +550,7 @@ the PLIC manages them. This is required for Linux.
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---
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## Phase 12 — A Extension (Atomics)
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## Phase 12 — A Extension (Atomics) [Hard stretch]
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What: Implement the RV32A atomic instructions: `lr.w` / `sc.w` (load-reserved /
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store-conditional) and the AMO ops (`amoswap.w`, `amoadd.w`, `amoand.w`,
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@@ -560,7 +578,7 @@ reservation set and bus become more involved.
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---
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## Phase 13 — Pipeline (Optional but educational)
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## Phase 13 — Pipeline (Optional but educational) [Hard stretch]
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What: Insert pipeline registers between your stages (fetch|decode|execute|
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memory|writeback). Handle data hazards (forwarding/stalling) and control
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@@ -578,7 +596,7 @@ must — and if you do, do it before DRAM/firmware work piles on. Re-running
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---
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## Phase 14 — SPI Flash Boot + DRAM
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## Phase 14 — SPI Flash Boot + DRAM [Overkill/hard]
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What: Add an SPI flash controller to boot from the on-board flash (instead
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of BRAM initialization). The Arty A7-100T has a 16 MB Quad-SPI flash; map
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@@ -601,7 +619,7 @@ keep.
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---
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## Phase 15 — S-Mode, U-Mode, Sv32 Virtual Memory
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## Phase 15 — S-Mode, U-Mode, Sv32 Virtual Memory [Overkill/hard]
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What: Add supervisor and user privilege modes. Implement Sv32 page table
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walking (two-level page tables, 4 KB pages). Add the `satp` CSR, page-fault
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@@ -619,7 +637,7 @@ modes round-trip via `mret` / `sret`.
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---
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## Phase 16 — Linux Boot Contract (SBI / Device Tree / ABI)
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## Phase 16 — Linux Boot Contract (SBI / Device Tree / ABI) [Overkill/hard]
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What: Lock down everything Linux expects at the moment of `kernel_entry`.
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This is a real subproject, not a footnote inside "port Linux".
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@@ -664,7 +682,7 @@ debugging exercise on a known-good ABI surface.
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---
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## Phase 17 — Linux
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## Phase 17 — Linux [Overkill/hard]
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What: Build a minimal RISC-V Linux kernel against the device tree and
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boot path defined in Phase 16. Build an initramfs with BusyBox. Load
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